1. Technical Field
The disclosure relates generally to integrated circuit fabrication, and more particularly, to a PFET having a tailored dielectric constituted in part by an NFET threshold voltage (Vt) work function tuning layer in a gate stack thereof and related methods and integrated circuit.
2. Background Art
Referring to FIG. 1, the best known self aligned process flows for complementary metal oxide semiconductor (CMOS) fabrication with the high dielectric constant (high-k) dielectrics and metal gate stack 10 use a dual field effect transistor (FET) threshold voltage (Vt) work function tuning layers 12, 14 to tune the threshold voltage of adjacent n-type metal oxide semiconductor (NMOS) region 16 (for NFETs) and p-type metal oxide semiconductor (PMOS) region 18 (for PFETs). The work function tuning layers 12, 14 have been developed to address instability caused by use of high-k dielectrics 11 with metals 13 in gate stack 10. NMOS region 16 and PMOS region 18 are typically formed in a silicon substrate 20 having doped N-well 22 and P-well 24 separated by an isolation region 26, e.g., a shallow trench isolation (STI) of silicon oxide. The formation of FET Vt work function tuning layers 12, 14 requires masking of one of the adjacent NMOS and PMOS regions to remove the other region's Vt work function tuning layer over one side. In particular, as illustrated, a p-type field effect transistor (PFET) Vt work function tuning layer 14 is formed over PMOS region 18, and a high-k dielectric 11 such as hafnium oxide (HfO2) is formed over both regions 16, 18. An NFET Vt work function tuning layer 12 is then deposited over both regions 16, 18, but removed over PMOS region 18 since the NFET Vt work function tuning layer 12 is undesirable for the PFET. NFET Vt work function tuning layer 12 typically includes lanthanum (La), magnesium (Mg), barium (Ba), strontium (Sr) and other rare earth metals while the PFET Vt work function tuning layer 14 typically includes undoped silicon germanium (SiGe). Patterning of gate stack 10 then completes the process. This process is costly to manufacture because of the two extra lithography steps and disadvantageously increases process variability due to the need for the removal of the Nfet Vt tuning layer from the PFET.